

#ifndef _MPI_VI_H_
#define _MPI_VI_H_

#ifdef  __cplusplus
extern "C"
{
#endif


#ifndef DIV_ROUND
#define DIV_ROUND(divident, divider)    (((divident)+((divider)>>1))/(divider))
#endif

#define SGKS_DSP_VFR(vfr)                     (vfr)
#define SGKS_DSP_VFR_INTERLACE(vfr)           (vfr|0x80)
#define SGKS_DSP_VFR_29_97_INTERLACE          SGKS_DSP_VFR(0)
#define SGKS_DSP_VFR_29_97_PROGRESSIVE        SGKS_DSP_VFR(1)
#define SGKS_DSP_VFR_59_94_INTERLACE          SGKS_DSP_VFR(2)
#define SGKS_DSP_VFR_59_94_PROGRESSIVE        SGKS_DSP_VFR(3)
#define SGKS_DSP_VFR_23_976_PROGRESSIVE       SGKS_DSP_VFR(4)
#define SGKS_DSP_VFR_12_5_PROGRESSIVE         SGKS_DSP_VFR(5)
#define SGKS_DSP_VFR_6_25_PROGRESSIVE         SGKS_DSP_VFR(6)
#define SGKS_DSP_VFR_3_125_PROGRESSIVE        SGKS_DSP_VFR(7)
#define SGKS_DSP_VFR_7_5_PROGRESSIVE          SGKS_DSP_VFR(8)
#define SGKS_DSP_VFR_3_75_PROGRESSIVE         SGKS_DSP_VFR(9)
#define SGKS_DSP_VFR_10_PROGRESSIVE           SGKS_DSP_VFR(10)
#define SGKS_DSP_VFR_15_PROGRESSIVE           SGKS_DSP_VFR(15)
#define SGKS_DSP_VFR_24_PROGRESSIVE           SGKS_DSP_VFR(24)
#define SGKS_DSP_VFR_25_PROGRESSIVE           SGKS_DSP_VFR(25)
#define SGKS_DSP_VFR_30_PROGRESSIVE           SGKS_DSP_VFR(30)
#define SGKS_DSP_VFR_50_PROGRESSIVE           SGKS_DSP_VFR(50)
#define SGKS_DSP_VFR_60_PROGRESSIVE           SGKS_DSP_VFR(60)
#define SGKS_DSP_VFR_120_PROGRESSIVE          SGKS_DSP_VFR(120)
#define SGKS_DSP_VFR_25_INTERLACE             SGKS_DSP_VFR_INTERLACE(25)
#define SGKS_DSP_VFR_50_INTERLACE             SGKS_DSP_VFR_INTERLACE(50)

#define SGKS_DSP_VFR_23_976_INTERLACED        SGKS_DSP_VFR_INTERLACE(4)
#define SGKS_DSP_VFR_12_5_INTERLACED          SGKS_DSP_VFR_INTERLACE(5)
#define SGKS_DSP_VFR_6_25_INTERLACED          SGKS_DSP_VFR_INTERLACE(6)
#define SGKS_DSP_VFR_3_125_INTERLACED         SGKS_DSP_VFR_INTERLACE(7)
#define SGKS_DSP_VFR_7_5_INTERLACED           SGKS_DSP_VFR_INTERLACE(8)
#define SGKS_DSP_VFR_3_75_INTERLACED          SGKS_DSP_VFR_INTERLACE(9)


typedef union
{
	u16 data;
	struct
	{
		u16 S_Control_reset                 :  1;   // 0: no op  1: reset video in
		u16 S_Control_enable                :  1;   // 0: idle   1: enable video in
		u16 S_Control_win_en                :  1;   // enable capture window. automatic reset at the end of each capture
		u16 S_Control_data_edge             :  1;   // Data clock edge. 0: valid on rising edge of sensor clock
		//                  1: valid on falling edge of sensor clock
		u16 S_Control_mastSlav_mod          :  2;   // Bit [5:4] forms the following combination:
		// 2b00: undefined
		// 2b01: slave mode
		// 2b10: master mode
		// 2b11: undefined
		u16 S_Control_data_emb_sync         :  1;   // sync code embedded in data. When set in master mode,
		// this indicates sensors have embedded sync code while
		// receiving seperate sync signals (Sony specific).
		u16 S_Control_data_emb_sync_mode    :  1;   // Embedded sync mode. 0: ITU-656 style(8-bit) 1: ITU-656 style(full data range)
		u16 S_Control_data_emb_sync_loc     :  2;   // Embedded sync code location (2-pixel wide input only).
		// 2b00: embedded sync code carried on the lower pixel
		// 2b01: embedded sync code carried on the upper pixel
		// 2b1x: embedded sync code carried on both pixels [should programed to 2b1x for serial sensor interface modes]
		u16 S_Control_data_vs_pol           :  1;   // vsync polarity. 0: active high (rising edge signals start)  1: active low (falling edge signals start)
		u16 S_Control_data_hs_pol           :  1;   // hsync polarity. 0: active high (rising edge signals start)  1: active low (falling edge signals start)
		u16 S_Control_data_field0_pol       :  1;   // 0: field 0 has ID set to 0 with wen assertion   1:field 0 has ID set to 1 with wen assertion
		u16 S_Control_data_sony_field_mode  :  1;   // 0: normal field mode   1: Sony-specific field mode. The first field of a multi-field readout in Sony CCD/TG is indicated by the state of EXP/ID pin at the first assertion of WEN/FLD
		u16 S_Control_data_ecc_enable       :  1;   // 656 error correction enable {including the sync code words in serial sensor mode]
		u16 S_Control_data_hsync_mask       :  1;   // 0: Toggle hsync during vertical blanking    1: No hsync toggle during vertical blanking
	} bits;
}sgks_vi_ctrl_reg_u;


typedef union
{
	u16 data;
	struct
	{
		// input mode[4:0]
		u16 S_InputConfig_pad_type          :  1;   // 0: LVCMOS  1: LVDS
		u16 S_InputConfig_data_rate         :  1;   // 0: SDR    1: DDR
		u16 S_InputConfig_data_width        :  1;   // 0: 1-pixel wide  1: 2-pixel wide [should be programed to 1 (2-pixel wide) for serial sensor interface modes]
		u16 S_InputConfig_input_source      :  1;   // 0: from LVDS (lvds_idsp_sdata)     1: from GPIO (iopad_idsp_sdata). Input source and pad type forms three combinations:-LVDS source, LVDS pad.-LVDS source, LVCMOS pad.-GPIO source. (Pad type makes no difference.)
		u16 S_InputConfig_RGB_YUV           :  1;   // 0: RGB input    1: YUV input
		// The following are legal combinations for input mode (x: 0 or 1, -: no effect):
		// x000x:SDR,1-pixel wide RGB/YUV data, from lvds_idsp_sdata[13:0]
		// x001x:DDR,1-pixel wide RGB/YUV data, from lvds_idsp_sdata[27:0]
		// x0100:SDR,2-pixel wide RGB/YUV data, from lvds_idsp_sdata[27:0]
		// x0110:DDR,2-pixel wide RGB/YUV data, from lvds_idsp_sdata[55:0]
		// 110--:1-pixel wide YUV data, from iopad_idsp_sdata[7:0]
		// 111--:2-pixel wide YUV data, from iopad_idsp_sdata[15:0]
		u16 S_InputConfig_Source_pixel_data_width   :  2;   // Source pixel data width. VIN aligns all pixel values to MSB at output.
		// For example, 8-bit source means left shift by 6, 14-bit source means no shift,
		// etc. YUV data coming from GPIO must be 8-bit wide. (Hardware ignores the configuration.)
		// 2b00: 8-bit  2b01: 10-bit    2b10: 12-bit    2b11: 14-bit
		u16 S_InputConfig_YUV_input_order   :  2;   // YUV input order
		// For 1-pixel wide YUV data
		// 00:Cr,Y0,Cb,Y1,
		// 01:Cb,Y0,Cr,Y1,
		// 10:Y0,Cr,Y1,Cb,
		// 11:Y0,Cb,Y1,Cr,
		// For 2-pixel wide YUV data
		// 00:{Cr,Y},{Cb,Y},
		// 01:{Cb,Y},{Cr,Y},
		// 10:{Y,Cr},{Y,Cb},
		// 11: {Y, Cb}, {Y, Cr},
		u16 S_InputConfig_Number_of_active_SLVS_lanes   :  2;   // Number of active SLVS lanes
		// 2b00: 4 lanes; 2b01: 8 lanes; 2b10: 12 lanes; 2b11: 16 lanes)
		u16 S_InputConfig_Serial_sensor_interface_mode  :  1;   // Serial sensor interface mode (Micron and Sony)
		u16 S_InputConfig_Sony_serial_sensor_interface_mode :  1;   // Sony serial sensor interface mode
		u16 S_InputConfig_VIN_clock_select  :  1;   // VIN clock select - use sensor or bit clock instead of IDSP clock
		u16 S_MIPI_Config                   :  2;   // reserved
	} bits;
} sgks_vi_inp_cfg_reg_u;

int sgks_mpi_vi_GetSensorCapability(sgks_vi_src_capability_s *vi_cap_ability);
int sgks_mpi_vi_EnalbeDevice(sgks_mpi_vi_device_s *vi_device, u32 *sensor_handle);
int sgks_mpi_vi_init(sgks_mpi_vi_device_s *vi_device);
int sgks_mpi_vi_GetFramerateTime(u32 fps);
void sgks_vi_Cmd_SensorConfig(sgks_mpi_manager_s *mpi);
int sgks_mpi_vi_Cmd_VideoPreProc(sgks_mpi_manager_s *mpi);
int sgks_mpi_vi_Cmd_CapWin(sgks_mpi_manager_s *mpi);
int sgks_mpi_vi_deinit();
int sgks_mpi_vi_OpenDeviceNode(sgks_mpi_manager_s *mpi);
int sgks_mpi_vi_isp_senseor(u32 id, u8 *arg, int size);
u32 sgks_mpi_vo_FpsFormatToVfr(u32 fps, u32 format);
int sgks_mpi_sys_ViBindVo(int vi_id, int vo_id);

//int sgks_mpi_vi_SetMirrorMode(int mirror_bayer);
//int sgks_mpi_vi_SetBayerPattern(int bayer_pattern);

//int sgks_mpi_vi_GetSupportResolution(SGKS_MPI_VI_RESOLUTION_S *resolution);
u32 sgks_mpi_vi_GetSensorID(void);





#ifdef  __cplusplus
}
#endif


#endif 


